The present invention is related to digital signals, and more particularly to methods and arrangements for use in analyzing digital signals and patterns therein as shared between two or more systems, devices, and/or components.
Electrical, optical, and/or electromagnetic signals are used to convey information amongst various interfaced systems, devices, and components. To properly convey such information these interfaced xe2x80x9cunitsxe2x80x9d need to adhere to an agreed upon signaling format, such as, an existing communication standard. There are a number of standards available for implementation. Choosing one will depend upon the needs of the units being connected, etc.
There is a continuing drive towards higher speed digital interfaces, ones that can support the ever-expanding information age. Recently, for example, high-speed Fibre Channel and Gigabit Ethernet interfaces have become popular choices for implementation between various units. In these exemplary standards, the clock signal required to receive the information being transmitted is embedded within the serial digital data stream. Once the clock signal is recovered by the receiving unit, then the additional information included in the digital data stream can be recovered. Errors will occur if the recovered clock signal does not significantly match the original clock signal of the sending unit. Such errors can severely reduce the performance of a high-speed interface.
One of the problems associated with digital signaling is an effect known as xe2x80x9cjitterxe2x80x9d. While technically speaking there are different types of jitter, jitter is often defined as the deviation from the ideal timing of an event. Thus, for example, jitter may cause an edge in a received digital signal to be altered in some fashion such that it is detected as occurring at an earlier or later time than it should be. For most interfaces, and especially high-speed digital interfaces, it is important to characterize and understand the amount/type of jitter affecting the digital data stream. Careful analysis of the jitter may lead to improvements in design, etc., of the interface and/or units.
Various test instruments are currently available for measuring and analyzing jitter. By way of example, the Wavechrest Corporation of Edina, Minn. produces several test sets that can be employed to characterize jitter in a digital interface.
For many interfaces, as is the case for high-speed Fibre Channel and Gigabit Ethernet interfaces, it is useful to generate specific test data streams that focus on certain jitter or other like degradation characteristics of the interface and/or units. In such a test arrangement, the receiving unit and/or connected testing device needs to know when to start and stop testing, recording and/or analyzing the received signal. This is often accomplished by an external arming signal, for example, from a signal generator. The arming signal may also be automated to synchronize to particular repeated signals.
It would be more useful, however, to have improved methods and arrangements that can be implemented to arm the testing device at a particular point in the data stream, because it has been found that the amount/type of jitter can vary depending upon the previous states of the interface. Thus, for example, if a digital data stream has been at a high binary level for several clock cycles, then a sudden change to a low binary level will typically occur later in time (i.e., resulting in more jitter) than would a more frequently alternating change between binary logic levels. Moreover, certain implemented data transmission channels introduce elasticity into the data stream that can cause problems for conventional test instrument arming techniques.
The present invention provides improved methods and arrangements that can be implemented to arm a testing device or other like units at a particular point in a data stream.
For example, the above stated needs and others are met by a method that includes receiving a serial digital data stream having a trigger pattern immediately preceding a test pattern, determining if a selected portion of the digital data stream matches a pattern mask, the pattern mask being logically associated with the trigger pattern, and outputting an arming signal upon determining that a match exists between the selected portion of the digital data stream and the pattern mask.
In certain instances, the method may further include selectively converting portions of the serial data stream into corresponding parallel bit words and logically comparing one or more parallel bit words with the pattern mask. In certain implementations, the method includes interfacing with a data transmission channel, such as, for example, a data transmission channel that employs standards associated with either Fibre Channel or Gigabit Ethernet.
The method may also include generating the serial digital data stream and activating a test instrument with the arming signal. The method may be implemented in hardware, firmware, software, or any combination thereof.
The method may be implemented in a stand-alone device, one or more integrated circuits, programmable logic devices, computer programs, etc., and/or integrated within a test instrument or any other unit or appliance.